Continuous risk scoring, hardware roots of trust, and agent-supervised EDA

BOM Management Is Moving Into Continuous Risk Scoring

Accuris is pushing BOM management out of late-stage spreadsheet review and into a continuous decision layer inside PLM and component-selection workflows. Its BOM Intelligence Platform adds a natural-language BOM Agent, an AI Health Agent for ongoing monitoring, automated risk scoring, feasibility and viability checks, and explainable part recommendations that weigh risk, cost, lifecycle, and compliance.

The platform also claims predictive obsolescence forecasting 12–36 months before official EOL notices, earlier detection of REACH, RoHS, PFAS, TSCA, Prop 65, sanctions, and tariff exposure, and alternate-part identification from a curated dataset of about 40 million parts. That is a clear break from traditional BOM tools, which mostly deliver static views, rule-based alerts, and reactive reporting. Similar moves from OpenBOM and Altium point in the same direction.

For hardware engineers and supply-chain teams, the practical shift is that component choice is becoming a live risk-management task, not a one-time sourcing exercise. The people who will benefit most are the ones who can use these systems to catch compliance and lifecycle issues earlier, defend design choices with evidence, and reduce redesign churn before parts lock-in.

Hardware Root of Trust Moves from Differentiator to Baseline

OpenTitan is the clearest proof that hardware security is becoming a baseline: Google’s open-source root of trust already ships in Chromebooks as a discrete chip that verifies firmware before startup, and LowRISC positions it as a reusable Apache 2.0 hardware RoT in two forms, Earl Grey for discrete devices and Darjeeling for SoC integration. The catch is that it is not a plug-and-play security layer; reuse still demands device-specific integration, provisioning, and changes to key storage and boot flows.

The EU CRA guidance turns “” into concrete engineering work this week. Teams now need hardware-rooted secure boot with cryptographic verification, authenticated updates, secure-by-default configuration, vulnerability monitoring through the declared support period, often at least five years, and technical documentation such as SBOMs and test evidence retained for 10 years for conformity and CE review. For hardware engineers, this shifts security from a late-stage review item to a design requirement that affects architecture, bring-up, manufacturing, and long-term support planning.

Verification Shifts from Manual Flow to Autonomous Compute

At DAC 2026, Synopsys and NVIDIA pushed verification in two complementary directions: one toward autonomous execution, the other toward faster compute. Synopsys unveiled an AI verification agent that can derive goals from specs, RTL, and test repositories, generate and refine test plans, orchestrate regressions, target coverage gaps with new tests, and assist debug through waveform, log, and source analysis. Synopsys says the system can cut time-to-validated RTL by up to 50× and improve coverage closure by about 20%.

NVIDIA answered on the infrastructure side with Vera CPUs, a verification compute platform for EDA workloads. It reported up to 1.5× speedups on selected Cadence Jasper formal and Synopsys VCS simulation workloads, driven mainly by stronger sustained per-core performance and higher-bandwidth memory rather than simply more cores. For verification engineers, the job is shifting in two directions at once: less time spent manually stitching together DV tasks, and more pressure to understand how agentic tooling and specialized compute change throughput, debug cadence, and coverage strategy.

EDA Work Moves from Tool Operation to Agent Supervision

Siemens and Synopsys have made the shift explicit: EDA is moving from manual tool operation to supervised agent workflows that plan, execute, verify, and iterate across the flow. Siemens’ Questa One now includes an RTL Code Agent for natural-language RTL generation and a Verification Planning Agent that derives plans from specifications, then extends autonomy into place-and-route, timing closure, power optimization, lint/CDC/debug, and coordination across Veloce emulation, Tessent DFT, and Calibre.

Synopsys is taking a narrower but production-focused path, using DSO.ai to tune placement, routing, timing, and PPA closure, while VCS AI Testbench generates tests to fill coverage holes; its debug workflows reportedly cut debug-cycle time by 25–40%. NVIDIA’s announcements point to the infrastructure layer for these long-running agents, with Nemotron models, NeMo Gym, and Switchyard/CUDA-X-style compute.

For hardware engineers, the job is shifting away from driving point tools and toward defining intent, constraints, checkpoints, and signoff criteria. Teams that can supervise agentic flows will move faster; teams that cannot will spend more time reacting to tool output than shaping design outcomes.