Package-Aware Co-Design Moves Upstream, EU Age Checks Put Hardware Attestation on the Hook

Package-Aware Co-Design Is Moving Upstream

Synopsys and Intel just certified AI-powered EDA implementation and signoff flows for Intel 14A, plus a 3DIC Compiler-based multi-die flow for Intel EMIB and EMIB-T. The key shift is “exploration-to-signoff” for multi-die systems: early multiphysics analysis now spans power integrity, thermal, and electromagnetic/signal effects, while packaging-aware planning covers bump and TSV placement plus automated UCIe and HBM routing. That pushes die, package, and interconnect decisions upstream, before tapeout, instead of handing them off in sequence.

Intel’s roadmap reinforces the same direction. EMIB-T adds TSV-based power delivery for higher-power AI and HPC scaling, while Foveros and Foveros Direct keep advancing 3D stacking and hybrid bonding. Intel’s glass-substrate packaging work with Lens Technology shows heterogeneous integration is being built around multiple bridge, stack, and substrate options, not a single packaging path.

For hardware engineers, the practical takeaway is clear: package constraints are no longer a downstream check. Teams that can co-optimize silicon, packaging, and routing earlier will iterate faster, reduce surprise signoff issues, and make chiplet architectures more predictable to ship.

EU Age-Verification Rules Put Hardware Attestation on the Hook

The EU age-verification specification now explicitly requires hardware-bound attestation, using native cryptographic hardware where available so credentials cannot be copied, cloned, or reused outside trusted hardware. Expected roots of trust include Apple Secure Enclave, Android TEE, and Android StrongBox, with attestation in ISO mDoc format. At the same time, the EU Cyber Resilience Act’s reporting clock starts on 11 September 2026: manufacturers must file an early warning within 24 hours, a full notification within 72 hours, and a final report within 14 days after a corrective measure is available, or within one month for severe incidents. CTC Union’s A402, A804/AG804, A1606, AG2404, AGS2404, and AMG2404 switch lines have also reached IEC 62443-4-2 SL2 with validated controls for authentication, access control, secure communications, data integrity, event logging, and unauthorized-access defenses.

Together, these signals push the hardware security story one step further: secure boot and key storage are no longer enough, because teams now have to prove hardware binding, requirement traceability, and regulator-ready incident handling. For hardware engineers, that extends the work from architecture and provisioning into verification, logging, and asset-to-version traceability, with tighter coordination across firmware, product security, and compliance as release planning starts to absorb evidence collection.