Agentic AI Orchestrates EDA Workflows, and Physical Test Topology Goes Software-Defined

Agentic AI Moves Into Specific EDA Workflow Orchestration

Synopsys, Keysight, and Nvidia gave the clearest evidence this week that agentic AI is entering named EDA workflows, not just generic design assistants. Synopsys pointed to chiplet floorplan co-optimization in 3DIC Compiler and agent capabilities for RTL and testbench generation, simulation planning, and verification/debug closure. Keysight added agentic AI for RF design in ADS 2027 and RF Circuit Simulation Professional, using MCP-based access to documented RF skills for simulation setup and iterative optimization. Nvidia’s $2 billion investment in Synopsys, tied to a broader partnership, reinforces the push to pair AI with GPU-accelerated engineering workflows.

The practical shift is narrower than a wholesale redesign of hardware engineering: vendors are packaging agents as orchestration layers for specific multi-step tasks inside design and verification flows. For engineers, that means the highest-value use cases are likely to be chiplet integration and RF simulation, where setup, optimization, and closure can be coordinated across tools and stages. Teams should expect pressure to standardize these workflows, because the people who can define, supervise, and validate agent-driven steps will shape how much leverage the tools actually deliver.

Physical Test Topology Becomes Software-Defined

Keysight this week launched the Velocity 4900 series Layer 1 Automation Switches, including the 4902 and 4906, to automate physical connectivity in hardware labs. The systems use a non-blocking optical-electrical-optical switching matrix to deliver software-controlled Layer 1 forwarding for Ethernet traffic from 100 Mbps to 100 Gbps, plus port tapping and one-to-many traffic replication for broader diagnostics and test coverage.

The practical shift is away from manual cable moves and bench-side reconfiguration toward programmable topology changes that can be triggered remotely or embedded in automated test runs. For hardware engineering teams validating PCIe, Ethernet, SerDes, and CPRI-based wireless or RAN systems, that turns repeated bring-up, link checks, and lab setup into software-controlled workflow steps, improving repeatability and throughput in shared labs.

For individual engineers, topology control is becoming part of the test stack. The people who gain the most leverage will be those who can combine hardware validation with orchestration, remote lab automation, and CI/CD-style verification workflows.