Capacity Becomes the Moat, Grid Access Becomes the Bottleneck, and Rules Tighten Across the Chain

HBM Supply Deals Turn Capacity Into the Moat

Micron’s warning that memory shortages could last multiple years, plus HBM price increases tied to tight supply and a richer HBM4/HBM4E mix, shows the market has moved from scarcity to rationing. Reports that Nvidia has already locked a massive HBM supply deal underscore the shift: AI buyers are no longer just purchasing chips, they are securing long-dated capacity. With SK hynix, Samsung, and Micron described as effectively sold out for 2026 and extending commitments into 2027 and beyond, the key question is who can contract for memory and packaging early enough to ship systems at all.

That extends last week’s bottleneck thesis into a more explicit capacity race. Broadcom’s 221% year-over-year AI chip revenue surge, Marvell’s alliance expansion, and reports of Amazon seeking investor funding for Nvidia chip purchases all point to the same pattern: compute access is being won through multi-year agreements, prepayments, financing vehicles, and custom silicon programs, not just product roadmaps. As HBM consumes scarce DRAM wafer capacity and advanced packaging remains tight, suppliers with HBM4/HBM4E exposure gain pricing power and customer leverage. For operators, procurement and financing are now strategic. For vendors and investors, value is concentrating in firms that can reserve, bundle, or guarantee scarce memory and packaging capacity first.

AI Capacity Is Becoming a Grid-and-Interconnect Race

South Korea put scale behind the constraint this week, unveiling roughly $900 billion of AI infrastructure spending centered on deployment capacity, not just chip demand: about $518 billion for four new memory fabs, $356 billion for AI data centers through 2035, and $52 billion for an HBM packaging hub. In the Honam cluster, authorities also fast-tracked utilities by letting SK hynix start fab construction while power and water are built in parallel, with initial transmission targeted for late 2028 at about 3.1 GW, rising to 6.3 GW, and initial water supply also due around 2028.

The same week, reports said AI data-center expansion is being delayed by power shortages, while JEDEC issued its first silicon photonics reliability standard, Singapore launched a major photonics R&D push, and Google deployed MEMS optical circuit switching. The market is moving from a pure compute race to a power- and interconnect-constrained systems race: access to accelerators matters less if fabs and clusters cannot secure grid interconnection, water, and lower-watt-per-bit networking.

For operators, the procurement target is the most deployable, power-efficient stack. For vendors and investors, value is shifting toward advanced packaging, silicon photonics, optical switching, and power-management products that convert constrained infrastructure into usable AI capacity.

OpenAI and Rapidus Show the Next Battleground Is Inference and Ecosystem Readiness

OpenAI’s reported “Jalapeño” inference ASIC, co-developed with Broadcom, shows hyperscalers are now selectively internalizing the inference stack where latency and performance per watt matter most. The key shift is not the end of merchant GPUs, but the emergence of LLM serving as a workload worth a multi-generation custom-silicon roadmap. Inference is persistent, cost-sensitive, and operationally central enough to justify deeper vertical integration.

Rapidus is positioning for that demand before its 2nm launch. This week it added four Malaysian design partners to its CORE ecosystem—GreatAsic Technology, Infinecs Systems, Oppstar Technology, and SkyeChip—and said it has already secured 2nm design relationships ahead of planned production in the second half of fiscal 2027. The competitive test for advanced nodes is now broader than process claims: foundries must assemble design enablement, IP, packaging, and customer integration early enough to win sockets.

The Marvell model points the same way, with co-development spanning chiplets, packaging, implementation, and production support. For operators, this extends the custom-silicon playbook into inference economics; for vendors and investors, value is shifting further toward ecosystem pull, packaging, and recurring co-design around 2nm programs.

U.S. Rules Expand From Diversion Cases to Process-Level Semiconductor Licensing

Washington has now turned China chip restrictions into a codified operating regime. The latest U.S. rules shift from Nvidia-specific performance thresholds to process-based controls that widen coverage across the supply chain: they add due-diligence and verification requirements, extend licensing to foundries and OSAT/packaging firms unless proof paths are met, and formalize limits on chipmaking tools capable of producing logic at 14 nm or finer. The framework also expands the Foreign Direct Product Rule to more Chinese entities, while allied discussions and U.S. proposals target older-generation DUV tools as a remaining route to near-frontier manufacturing.

That is a step beyond the diversion enforcement seen last week. The issue is no longer just stopping misrouted GPUs; exporters now have to prove end use and traceability through manufacturing, packaging, and customer compliance. Applicants may need to show exports will not reduce U.S. semiconductor capacity, that Chinese customers have screening and export-compliance procedures, and that products passed independent U.S. third-party testing. For operators and vendors, the edge shifts further toward firms that can document end use across the chain. For investors, the split is widening between policy-exposed hardware and tool revenue and more durable software, IP, and licensing models.