Silicon photonics surge: AI data centers drive $144b boom

The global optical interconnect market is on track for a staggering tenfold expansion by 2030, soaring to an estimated $144 billion from under $14 billion in 2024. This explosive growth is largely fueled by the rapid adoption of silicon photonics and co-packaged optics (CPO) technologies, which together are expected to command nearly two-thirds of the market revenue. China Insights Consultancy and other analysts highlight the data center interconnect segment as a key driver, projecting a 48% compound annual growth rate that underscores the transformative impact of these technologies on AI networking infrastructure.

AI's insatiable demand for faster, more efficient data center connectivity is propelling the optical networking market to unprecedented heights, with Goldman Sachs forecasting a leap from $15 billion in 2024 to $154 billion by 2028. Central to this surge is co-packaged optics, anticipated to capture 59% of AI networking expenditures by 2028, reflecting its critical role in reducing power consumption and enabling high-speed, long-distance data transmission. Marvell Technology, commanding 60-65% of the optical digital signal processor market, is poised to capitalize on this trend with expected data center interconnect business growth exceeding 70% by fiscal 2027.

Silicon photonics is rapidly transitioning from a niche research domain to a mainstream semiconductor supply chain staple, driven by surging AI, cloud, and telecom demands. With revenues from silicon photonic integrated circuit dies growing at a robust 45% CAGR and wafer consumption dominated by silicon photonics transceivers at over 83%, the market is projected to surpass $1.865 billion by 2033. This shift necessitates scalable manufacturing and supply chain resilience, as companies like Marvell integrate silicon photonics platforms to support both traditional and co-packaged optics implementations, enabling the next generation of AI networking infrastructure.

The broader semiconductor industry is entering a 'giga cycle' fueled by massive AI infrastructure investments, intensifying the need for advanced optical interconnects that outperform traditional copper connections. Photonics technologies, leveraging light to transmit data faster and with less power over longer distances, are becoming indispensable for scaling AI systems. This paradigm shift not only accelerates market growth but also redefines networking architectures, positioning silicon photonics and CPO as foundational technologies for the future of high-performance computing and data center connectivity.

Marvell has emerged as a dominant force in the silicon photonics space, commanding a 60-65% share of the PAM4 DSP market critical for high-speed AI data center interconnects. Its Ara DSP on 3nm silicon, the industry's first 1.6T PAM4 DSP, enables simultaneous 200 gigabit per lane transmission on electrical and optical fronts, positioning Marvell to capitalize on the surging demand driven by evolving AI architectures that increasingly shift computational loads toward communication fabrics. With interconnect revenue growth projected above 70% year over year for fiscal 2027, Marvell is strategically expanding partnerships with AI infrastructure leaders like Nvidia, aiming to double scale-out switch revenue to over $1 billion by fiscal 2028 and solidify its leadership in both NPO and CPO technologies.

Nvidia is aggressively scaling its AI networking capabilities through mass production of its Spectrum-X co-packaged optics (CPO) switches, which deliver fivefold lower power consumption and dramatically improved signal integrity, fueling a 199% surge in networking revenue to $15 billion. This strategic pivot not only addresses critical bottlenecks in large AI clusters but also creates a 'sticky' ecosystem by integrating optics directly onto switch chips, encouraging hyperscalers to adopt Nvidia’s broader InfiniBand, NVLink, and Ethernet roadmap. Nvidia’s close collaboration with TSMC, which is expanding its CPO manufacturing and testing capacity, and investments in key suppliers like Coherent, underscore a tightly integrated supply chain geared toward silicon photonics leadership and ecosystem control.

SK hynix is charting a transformative course beyond its high-bandwidth memory roots by aggressively investing in co-packaged optics to overcome the 'bandwidth wall' created by the slower growth of interconnect bandwidth relative to computing performance. Its visionary roadmap, published in Nature Electronics and developed in collaboration with leading academic institutions, envisions an 'optics-centric' AI architecture where optical interposers directly connect pools of processors and memory, enabling shared memory access across thousands of nodes with over 100 Tb/s bandwidth per node at sub-picojoule energy efficiency. Backed by a robust $28.7 billion share repurchase program, SK hynix is poised to lead the system-level integration of optics closer to silicon, mirroring the revolutionary impact of HBM on memory proximity.

TSMC is leveraging its COUPE platform to integrate silicon photonics with advanced packaging technologies, aiming to dominate the optical chip market much like its leadership in AI packaging. By combining electronic logic, mature photonics processes, and 2.5D CoWoS integration, TSMC’s BOE architecture achieves significant power efficiency gains—reducing consumption by 40% or boosting speed by 170% compared to traditional microbump packaging—while its vertical optical coupling approach enhances fault tolerance against chip warpage. This meticulous process control and system-level innovation position TSMC as a critical enabler of scalable, high-bandwidth optical interconnects for AI and HPC applications, supporting industry leaders like Nvidia in their CPO ambitions.

Co-packaged optics (CPO) technology is revolutionizing high-performance computing and AI workloads by replacing traditional electrical interconnects with photonic channels, thereby overcoming fundamental limits in bandwidth, latency, and energy efficiency. SK hynix and other industry leaders target ambitious performance metrics such as over 100 Tb/s bandwidth per node, energy consumption below 1 picojoule per bit, and chip-to-chip latency under 10 nanoseconds, addressing the growing 'bandwidth wall' created by the disparity between compute performance growth and slower interconnect bandwidth scaling. This optical approach minimizes resistive losses and signal distortion inherent in copper wiring, enabling high bandwidth density and superior signal integrity essential for next-generation AI infrastructure.

The path to scaling CPO involves a complex evolution from 2D packaging to 2.5D interposer-based integration and ultimately 3D heterogeneous stacking, which facilitates closer chip placement and the extension of optical links directly to memory. SK hynix envisions an optics-centric architecture where multiple AI accelerators share a pooled memory space via optical interposers, enabling flexible system-level data movement and accommodating the exponential growth of AI models. However, these advances introduce significant commercialization and integration challenges, including thermal management, manufacturability, and standardization hurdles that must be overcome to establish CPO as foundational in HPC infrastructure.

Despite its transformative potential, CPO remains at an early stage of industrialization with unresolved challenges such as integrating low-power optical devices, ensuring data consistency and reliability, and managing power consumption and manufacturing complexity. These hurdles have confined initial commercial deployments to proprietary switching platforms operated by vertically integrated players capable of absorbing associated risks. Meanwhile, the optics module industry struggles to keep pace with the explosive demand driven by AI model growth—roughly 100-fold every two years—necessitating a roughly 70-fold increase in interconnects that current production capacities cannot yet sustain.

The shift in AI workloads has transformed photonics from an optional enhancement into a system-level requirement, as communication infrastructure now constitutes the primary bottleneck rather than compute power. Industry analysts like Martin Vallo of Yole Group emphasize that the evolution of optical transceivers is progressing from pluggable optics toward co-packaged optics, moving optical conversion increasingly closer to GPU and CPU packages. This transition is critical to meeting the stringent bandwidth and energy efficiency demands of next-generation AI data centers, underscoring the strategic importance of CPO in future semiconductor and networking ecosystems.

FOCI's pivotal role in TSMC's co-packaged optics (CPO) supply chain underscores the critical importance of fiber array units (FAUs), where precision and yield directly influence packaging scalability. Addressing manufacturing challenges such as thermal expansion and heat tolerance—since packaging processes now exceed traditional telecom temperature ranges—FOCI has integrated semiconductor and packaging expertise by recruiting industry veterans like TSMC's D.D. Hu, enabling advanced nanometer engineering solutions that maintain optical signal integrity under harsh conditions.

The rapid evolution of the CPO supply chain is marked by aggressive ecosystem standardization and integration efforts from semiconductor giants including NVIDIA, SK Hynix, TSMC, Samsung, GlobalFoundries, AMD, and Intel. These players are expanding production capacities and refining technology roadmaps to support system-level AI architectures that tightly couple optical links between processors and memory, demanding sophisticated supply chain coordination and fostering a shift from chip-level to holistic system competition.

Coherent emerges as a linchpin supplier within the CPO ecosystem, offering a comprehensive portfolio spanning high-power indium phosphide lasers to complete optical transceivers, which are essential for manufacturing and packaging innovations in AI data centers. This breadth of components supports the industry's push to integrate photonics closer to processors and memory, reducing electrical signal distances and power consumption, thereby enabling scalable, energy-efficient co-packaged optics production.

Manufacturing and packaging innovations are accelerating CPO deployment, with TSMC's COUPE platform exemplifying integration of advanced electronic logic, mature photonics processes, and wafer-level vertical optical coupling to enhance manufacturability and fault tolerance against chip warpage. Complementing this, Kulicke & Soffa's Thermo-Compression Bonding (TCB) and Fluxless Thermo-Compression (FTC) technologies provide the precision and interconnect quality necessary for high-density heterogeneous integration, meeting the complex assembly demands driven by AI networking growth and enabling scalable, high-bandwidth semiconductor supply chains.