Silicon quantum chips hit milestones in scalable error correction

By mid-2026, Diraq and imec achieved a landmark breakthrough by fabricating an eight-qubit silicon spin qubit array entirely within a commercial 300 mm SiMOS CMOS foundry, proving that scalable, uniform quantum dot configurations can be produced at volume without compromising coherence or gate control. This modular device architecture, built on isotopically purified silicon with overlapping polycrystalline silicon gates, demonstrated coherence times (Ramsey dephasing up to 41 µs and Hahn-echo coherence exceeding 1 ms) on par with delicate academic cleanroom devices, validating the quality and reproducibility of foundry-scale manufacturing.

Innovations in readout architecture played a pivotal role in scalability, as Diraq and imec implemented a novel cascaded charge-sensing scheme leveraging Pauli spin blockade to trigger electron cascades, enabling compact, efficient readout of central qubits without a proportional increase in wiring or thermal load. This design addresses a critical bottleneck in scaling qubit arrays, maintaining manageable sensor counts and wiring density even as qubit numbers grow, a challenge that has historically hindered larger quantum processor development.

The seamless scaling from two to eight qubits on the same 300 mm CMOS platform without any loss in coherence or control fidelity marks a significant industrial milestone, underscoring the viability of leveraging mature semiconductor manufacturing infrastructure for quantum computing. As Dirac’s CEO Andrew Dzurak emphasized, this achievement exemplifies an industrial pathway toward quantum processors with thousands of qubits by 2029 and over a million by 2031, highlighting a roadmap that combines advanced CMOS technology with quantum device engineering to realize commercial-scale, error-corrected quantum computing.

Beyond qubit quality, imec stresses that the future of quantum computing hinges on the ability to manufacture increasingly complex quantum processors with the reproducibility, yield, and scale characteristic of the semiconductor industry. Diraq’s silicon spin qubits not only achieve high single- and two-qubit gate fidelities exceeding 99% but also operate above 1 kelvin, significantly easing cooling requirements and enabling tighter integration with control electronics—factors critical for manufacturability and scalability toward millions of qubits on standard 300 mm CMOS wafers.

HRL Laboratories has pioneered a silicon quantum processor integrating an 18-qubit array with a custom cryogenic CMOS controller operating at temperatures as low as 4 Kelvin, enabling fully autonomous quantum error correction without reliance on external room-temperature electronics. This breakthrough architecture completes quantum operations in under a microsecond and achieves a tenfold reduction in control errors compared to previous efforts, marking a significant leap in both speed and precision of quantum control.

Central to HRL's innovation is a high-density superconducting ribbon cable that transmits hundreds of control signals to qubits while minimizing heat transfer, effectively addressing the longstanding wiring complexity and thermal management challenges that have hampered scalability in quantum computing. By situating the CMOS controller chip within the cryostat near absolute zero, HRL eliminates the disruptive thermal noise from warmer electronics, simplifying system architecture and paving the way for scaling to thousands or even millions of qubits.

HRL's demonstration of error correction performance reveals a roughly fivefold reduction in errors as the number of qubits in their repetition code increases, validating theoretical models and underscoring the scalability of their integrated control approach. While the current implementation employs a repetition code rather than full fault-tolerant error correction, the results strongly support the feasibility of manufacturable, scalable quantum processors built using standard microchip production lines, all housed within a single refrigerator to reduce costs and complexity.

Diraq's establishment of a new engineering hub in Santa Monica marks a strategic expansion of its global R&D network, designed to tightly integrate silicon spin-qubit arrays with cryo-CMOS control electronics. By situating this multidisciplinary facility in Southern California, Diraq leverages the region's semiconductor expertise to pioneer integrated circuits that combine qubit drive, readout, and multiplexing directly on a single silicon die. This integration not only minimizes the thermal load and interconnect complexity traditionally caused by thousands of coaxial cables in dilution refrigerators but also accelerates the path toward scalable, fault-tolerant quantum processors.

Diraq’s trans-Pacific engineering framework, spanning hubs in Sydney, Palo Alto, Santa Monica, and Chicago, exemplifies a coordinated global approach to scaling silicon spin-qubit technology from isolated device demonstrations to fully fault-tolerant systems. This geographically distributed design capability harnesses diverse expertise and resources, enabling the company to maintain momentum toward its ambitious goal of launching a commercial quantum product by 2029. The synergy between these hubs facilitates rapid iteration and integration across hardware and software stacks, underscoring Diraq’s commitment to bridging the gap between laboratory breakthroughs and market-ready quantum computing solutions.