Silicon spin qubits gain industrial capacity

Silicon spin qubits stand out in the quantum computing landscape due to their seamless integration with the mature CMOS manufacturing infrastructure, leveraging decades of semiconductor process optimization. This compatibility not only enables the use of existing industrial ecosystems but also aligns quantum scalability with classical miniaturization principles, allowing future quantum processors to scale from tens of thousands to potentially tens of millions of qubits within manageable power and infrastructure constraints. Such scalability is critical for transitioning quantum computing from experimental setups to utility-scale high-performance computing (HPC) systems.

Despite current silicon spin qubit devices being limited to qubit counts in the upper teens, industry leaders remain optimistic about their potential, projecting ambitious targets of millions or even billions of qubits per chip. This optimism is bolstered by demonstrated gate fidelities exceeding 99% on 300mm industrial wafers, positioning silicon spin qubits as a formidable contender to eventually surpass superconducting qubits as the preferred low-temperature, chip-oriented quantum computing modality.

One of silicon spin qubits’ unique strengths lies in their diversity of submodalities and intrinsic compatibility with CMOS technology, which is unmatched among the four major quantum modalities. This variety not only broadens the technological pathways for implementation but also underpins a pragmatic, industrially scalable approach dubbed 'The CMOS Path to Quantum Computing,' emphasizing manufacturability and integration as cornerstones for future quantum systems.

In July 2026, Diraq and imec marked a pivotal scaling milestone by demonstrating the first coherent operation and readout of an eight-qubit silicon MOS spin-qubit array fabricated entirely using imec’s advanced 300mm CMOS-compatible semiconductor manufacturing process. This achievement extended beyond previous two-qubit devices, showcasing a significant leap toward industrial quantum hardware by leveraging nearly a decade of process optimization to bridge laboratory prototypes with scalable, manufacturable quantum processors.

The eight-qubit device maintained exceptional coherence and control, with Ramsey dephasing times reaching up to 41±2 μs and Hahn-Echo coherence times up to 1.31±0.04 ms, rivaling or exceeding those from specialized academic cleanrooms. This validation of industrial fabrication was achieved without increasing sensor count, wiring density, or thermal load, thanks to a novel cascaded charge-sensing readout architecture and the use of isotopically purified 28Si substrates with a triple-layer polycrystalline silicon gate stack, which together enhanced qubit performance while preserving manufacturability.

Executives from Diraq and imec framed this breakthrough as a clear 'industrial pathway' to quantum computing, with Diraq’s CEO Andrew Dzurak highlighting the rapid progression from initial fabrication to scaling without compromising coherence. The roadmap ambitiously targets scaling from hundreds of qubits to over a million by 2031 using the same compact CMOS manufacturing approach, underscoring industry confidence that semiconductor-grade reproducibility, yield, and scale are now within reach for complex quantum processors.

In a landmark government-backed initiative announced in July 2026, Hitachi, Intel, and AIST secured funding from Japan's NEDO to spearhead the development of silicon quantum processors scaling up to 1,000 qubits by 2030. This collaboration leverages Hitachi’s industrial implementation expertise, Intel’s semiconductor manufacturing prowess, and AIST’s research capabilities to transition silicon spin qubits from laboratory prototypes to industrial-scale quantum computing infrastructure, targeting transformative applications in pharmaceuticals and energy logistics. Hitachi CTO Shigetoshi Samejima emphasized quantum computing's critical role in overcoming conventional computational limits and supporting future social and industrial infrastructure.

Central to this initiative is the adoption of Intel’s cutting-edge 18A semiconductor process, which entered high-volume manufacturing in late 2025 and incorporates RibbonFET and PowerVia technologies that enhance transistor uniformity and power delivery—key factors for qubit fidelity and routing density. The project aims to deliver a 100-qubit prototype by fiscal 2028 and launch a cloud-based experimental quantum service by fiscal 2027, underscoring a strategic roadmap toward scalable silicon spin qubit mass manufacturing.

Beyond hardware, the consortium is building a comprehensive engineering stack—including chip designs, manufacturing toolkits, cryogenic packaging, and cloud infrastructure—to enable industrial-scale production rather than isolated demonstrations. A pivotal deliverable is the creation of the first quantum process design kit (PDK) tailored for a 1.8nm-class semiconductor node, which will democratize silicon spin-qubit chip design by allowing external teams worldwide to fabricate quantum hardware on industrial fabs without reconstructing manufacturing knowledge from scratch. This PDK is envisioned as a catalyst for ecosystem growth, fostering global accessibility and innovation.

The initiative is structured around four interlocking workstreams that address scalable chip architecture, quantum PDK development, 3D cryogenic integration to surmount wiring bottlenecks, and an open cloud platform operated by AIST’s G-QuAT facility for remote quantum hardware access. This multifaceted approach reflects a strategic commitment not only to mass manufacturing but also to ecosystem democratization, positioning Japan at the forefront of silicon spin qubit quantum computing development.

By mid-2026, Imec and Diraq researchers had harnessed extreme-ultraviolet (EUV) lithography—originally developed for high-volume semiconductor manufacturing—to fabricate high-fidelity SiMOS spin qubits with nanometer precision. This approach overcame the limitations of electron-beam lithography, achieving gate fidelities nearing fault-tolerant thresholds (up to 99.9% SPAM, 99.8% single-qubit, and 99.5% two-qubit gates) while enabling sub-nanometer control over gate dimensions and reproducible exchange turn-on characteristics critical for scalable quantum processor production.

Simultaneously, Argonne National Laboratory, in collaboration with Intel, mapped atomic-scale fluctuations within silicon quantum well layers that cause variability in valley splitting—a key factor undermining silicon spin qubit stability. This breakthrough transformed valley splitting from a mysterious barrier into a tangible materials engineering challenge, opening clear pathways for targeted refinement to enhance qubit fidelity and stability on industrial-grade silicon wafers.

By mid-2026, SLAC researchers, led by scientist Shannon Harvey, made significant strides in tackling the persistent challenges of noise and interference that undermine the stability and scalability of quantum dot qubits. Their work underscores the critical need for an interdisciplinary approach, blending materials science, physics, computer science, and engineering to create an environment where millions or even billions of qubits can operate harmoniously on a single chip. Harvey emphasizes that while quantum dots hold immense promise for scalable quantum computing, mitigating energy fluctuations caused by noise remains essential to preserving qubit fidelity and enabling reliable mass manufacturing.

In a significant stride toward the elusive million-qubit quantum computer, scientists have proposed a novel chip architecture aimed at overcoming key scaling barriers, signaling a pivotal evolution in quantum hardware design. This architectural innovation aligns with parallel advances in qubit technology, such as HRL Laboratories' demonstration of a scalable quantum dot system that manipulates three interacting electron spins electronically—eschewing traditional microwave controls—and achieves a logical error rate below 1% on an 18-qubit platform. These developments collectively underscore a shift toward more practical and scalable silicon-based qubit implementations, blending architectural ingenuity with refined qubit control techniques.

The race to scale quantum computing hardware is further energized by substantial financial backing, exemplified by GlobalFoundries securing a $300 million CHIPS award to propel silicon photonics research critical for scalable quantum technologies. This infusion of capital not only accelerates the development of advanced chip architectures but also reflects growing industrial confidence in silicon-based quantum platforms as foundational to future quantum processors capable of handling millions of qubits.

Meanwhile, the quantum landscape is diversifying with IBM's strategic acquisition of HRL Laboratories' quantum dot technology, marking a notable pivot from their established superconducting transmon qubits toward silicon-based alternatives that promise enhanced scalability and error rates. Complementing this, emerging platforms such as diamond vacancy qubits—demonstrated by a company showcasing a processor with 100 electrons trapped in diamond defects—expand the horizon of qubit modalities, suggesting that the quest for scalable quantum computing will likely embrace a heterogeneous mix of architectures and materials.